The KL-10 (in DECSYSTEM-20) introduced in 1974 was a 36-bit word size, magnetic core (later semiconductor) memory, capacity of 32K to 4096K (4M) words 500 nanosecond instruction cycle, 1.8 MIPS CPU. The fast speed was partially possible due to the cache memory technology.
Magnetic core memory. 1951 Jay Forrester filed a patent application for the matrix core memory. Core memory was born
The I/O cabinet connected the main processor KL10 to the peripherial devices via MASSBUS or UNIBUS (see the following picture). MASSBUS was for fast and large amounts of data transfer and UNIBUS was for slow terminals, printers and similar.
As already told before in this article series the DECSYSTEM-20 (PDP-10 / KL10) was delivered in 3 cabinets as seen in the following picture. The front end processor (PDP-11/40) was located in the number 1 cabinet, the left most, with the expansion drawer to hold application specific variable system parts. The whole system could have more than 3 cabinets if more space was required.