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Apr 6, 2014

Digital's DECSYSTEM-20 - Part 5 - CPU (KL10)

CPU CABINET - Cabinet # 3 (Part 5)

The  KL-10 (in DECSYSTEM-20) introduced in 1974 was a 36-bit word size, magnetic core (later semiconductor) memory, capacity of 32K to 4096K (4M) words 500 nanosecond instruction cycle, 1.8 MIPS CPU. The fast speed was partially  possible due to the cache memory technology.

Magnetic core memory. 1951 Jay Forrester filed a patent application for the matrix core memory. Core memory was born

Intel 1101 (C1101) Static RAM Chip

1101 die. In 1969 Intel introduced the 1101, a 256-bit static RAM. This was the world's first high-volume MOS semiconductor memory, and the first use of MOS silicone gate technology.

The KL-10 was a new implementation of the PDP-10 (KA-10) architecture intended for high-end time sharing in data centers. It was built using a fast but power-hungry technology called emitter-coupled logic (ECL), which was soon replaced by other methods of making logic components that used far less power but offered even higher speed.

Although the KL-10 was intended for the new TOPS-20 operating system, which provided more powerful tools for system developers, customers demanded that DEC provide a version of Tops-10 for the DECsystem-20 because of its more efficient use of resources. The improved quality of system services under TOPS-20 reduced the number of users it could support. TOPS-20 was developed by DEC.

The blue areas in the following block diagram show the 3 cabinets again. The CPU was situated in the cabinet # 3.

DECSYSTEM-20 block diagram

Each box in the block diagram is one or more Printed Circuit Boards (PCB's). The CPU cabinet was populated by the CPU logic IC boards and optionally memory modules. Earlier models had MA20 or MB20 memory blocks inside the cabinet but later models could use cache memories and the actual memory 2 x MF20 for example was actually in the cabinet # 2 (with I/O circuits, see previous part of this article).

LIST OF PARTS (see block diagram above)

Cabinet # 3: CPU and memory
  • KL10  -  Third PDP-10 CPU (ECL logic) used in 108x/109x/2040/2050/206x
  • MA20  -  32-256KW 1.0us parity internal memory

Here are some of those memory options listed.
  • MA20 32-256KW 1.0us parity internal memory (2 ctrls w/ 4 modules of 32K)
  • MB20 64-512KW 1.2us parity internal memory (2 ctrls w/ 4 modules of 64K)
  • MCA20 pager/cache memory (109x/2060)
  • MCA25 pager/cache memory (2065)
  • MF20 256K-1563KW 667ns ECC (36+6ECC+1parity+1spare) internal MOS (16K chips)
  • MG20 1-4MW 467ns ECC (36+7ECC+1spare) internal MOS (64K chips)

The cabinet was made so that there was an easy access to the back plane of the inserted PCB cards. Additional to the PCB racks the cabinets usually contained power supply boxes and  various cooling elements like fans and ducts.

Add caption
Front view of the DECSYSTEM-20 CPU (KL10) cabinet.

Rear view of the DECSYSTEM-20 CPU (KL10) cabinet. Lowest are power supplies and batteries.

The following picture lists all the parts in the CPU rack.

CPU modules or PCB's

PDP computers had easy access to the back plane which was wire wrapped. Wire wrapping of the back plane allowed to do easy modifications to any computer

Open wire wrapped back planes for easy modifications and access

Open wire pins at the back allowed easy testing and maintenance of the computer. Since they were wrapped they could easy be unwrapped and reconnected, thus allowing the modification of any individual computer.

Two men scoping DEC computer

OK Industries wire wrapping tools demonstrate how to make and unmake the connections at the back plane.


The TTL/Schottky (TTL/S) (Transistor Transistor Logic) series was first available in production quantities at about the time of the KI10. The KI10 (KL10 predecessor)design was started earlier and design options chosen so as to preclude the subsequent advances in speed, power, and density that the TTL/S gave.

The other important logic advances employed in the KI10 were the MSI register file and associative memory packages. The register file provided four sets of accumulators and thus decreased the context switching time. (This probably had a higher psychological than real value but was useful where special devices were operated on a high speed, real-time basis.) The associative memory package permitted the construction of a 32-word associative memory to support a paged environment. /3/

The KL10 provides almost a factor of 5 performance improvement over the KA10 for programs using the basic instruction set. An even larger performance improvement is realized for COBOL or extended precision scientific programs. The organization and much of the base work for the KL10 was done by Dave Poole, Phil Petit, John Holloway, and Jack Wright at the Stanford Artificial Intelligence Laboratory.

DEC Team, Gordon Bell third from left, and Alan Kotok fourth from left, with unidentified people next to the DEC PDP-6 (the first 36-bit PDP)

The KL10 is microprogrammed using a memory based on the 1 Kbit bipolar RAM. A cache memory is also constructed from the 1 Kbit chips. The KL10 is implemented in the emitter coupled logic (ECL) 10K series rather than in the TTL/Schottky of the original Stanford design. It was felt that the ECL speed advantage with 3 nanoseconds gate delay versus 7 nanoseconds for Schottky was worth the extra design effort especially because the ECL required more power and care to lay out the board and backplane.


The Gardner-Denver automatic Wire-wrap machine represented a significant advance in the manufacture of machines. Automatic Wire wrap economically provided accurately wired backpanels. As a more important side effect, it made the high-volume, low-cost fabrication of minicomputers possible! Some backpanel wiring on the KI10 and KL10 processors using twisted pairs cannot be done using the Gardner- Denver machinery. For this, DEC developed a semiautomatic wire-wrap machine which locates the pins and selects the wire length for an operator.

Gardner Denver wire wrap machine ca. 1965

Computer design aids have evolved to support computer implementations on an "as-needed" basis, barely keeping ahead of the implementations. These have included printed circuit board layout/routing, backplane layout/ routing, circuit/logic simulation, wire length/logic delay checking, and various manufacturing aids. One notable exception to this trend has been the Stanford University Drawing System (SUDS) developed by the Stanfortd Artificial Intelligence Laboratory.

This machine could wrap approximately 125 wires per min of 24 to 30 AWG over a 24" x 40" area.

Gardner Denver Corporation, founded in 1859, is a major manufacturer of heavy industrial equipment. In the early 1960's, Gardner Denver also developed the wire-wrap machine. In the decade following 1965, wire-wrap technology was probably the dominant technology for wiring the backplanes of both mainframes and minicomputers. Burroughs, Digital Equipment Corporation and IBM were among the major users of wire-wrapped backplanes. One of the (last) major systems to use wire-wrap technology was the Patriot anti-missile system that was the center of much publicity during the Persian Gulf War.

Patriot anti-missile system used wire-warp technology

In use, the wiring pattern of a backplane would be specified by a deck of punched cards, where each card gave the coordinates of the start and end of one wire. The Gardner Denver 14F wire-wrap machine was fully automatic, but not always successful -- the operator was responsible for noticing when it miswrapped a connection and correcting the problem. Earlier wire-wrap systems were semi-automatic; in those, the wire-wrap machine would automatically cut and strip the wire and position the wire-wrap tool over each pin to which the wire was to be connected; the operator would then handle the fine details of pressing the tool onto the pin before the machine finished wrapping the wire in place. However wire-wrap connetions were made, the result was a highly reliable solderless joint. /2/


Semiconductor density was a major determinant of the system size, and size in turn was (and is) a major determinant of speed (e.g., shorter interconnection paths). Seymour Cray stated in a lecture given at Lawrence Livermore Laboratory (December 1974) that for each generation of his large computers, the density has improved by a factor of 5.

Seymour Cray (Cray super computers) talking 1976

The packaging for the PDP-6 (the first 36-bit PDP) was identical to that of the PDP-l, 4, and 5 and used a board area of about 40 in2 with a 22-pin connector. A logic density improvement of 2 was achieved over the previous designs by using 6 special function modules. However, this density turned out to be too high for the number of pins. A natural extension was a board twice as large with 44 pins. The most interesting module was the bit-slice of the working registers: Accumulators, Multiplier-Quotient, and Memory Buffer.

This module required more than 44 pins, so the extra signals were bused across the back of the module. This busing increased module swap time, and the mechanical coupling increased the probability that fixing one fault would cause another. Because of this, the designers of the KA10 and KI10 became fearful of large boards. Only with the KL10 in 1972 were large boards reintroduced into the DECsystem-10. On the other hand, large boards had been used in DEC minicomputers since 1969. Multilayered boards were required for the KL10 ECL logic. These boards were adapted from the multilayered boards developed for the TTL/S PDP-l 1/45 (1972).

[The next part of the article will cover the power supplies.]


/1/ MP01708_KL10-R_System_Drawings_Sep83.pdf




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